mpc755 and mpc745 powerpc microprocessors are high-performance, low-power, 32-bit implementations of the powerpc reduced instruction set computer (risc) architecture, specially enhanced for embedded applications. mpc755 and mpc745 microprocessors differ only in that the mpc755 features an enhanced, dedicated l2 cache interface with on-chip l2 tags. the mpc755 is a drop-in replacement for the award winning powerpc 750 microprocessor and is footprint and user software code compatible with the mpc7400 microprocessor with altivec technology. the mpc745 is a drop-in replacement for the powerpc 740 microprocessor and is also footprint and user software code compatible with the powerpc 603e microprocessor. mpc755/745 microprocessors provide on-chip debug support and are fully jtag-compliant. superscalar microprocessor mpc755 and mpc745 microprocessors are superscalar, capable of issuing three instructions per clock cycle (two instructions + branch) into six independent execution units: two integer units load/store unit double-precision floating-point unit system register unit branch processing unit the ability to execute multiple instructions in parallel, to pipeline instructions, and the use of simple instructions with rapid execution times yields maximum efficiency and throughput for mpc755 and mpc745 systems. power management the mpc755 and mpc745 microprocessors feature a low-power 2.0-volt design with three power-saving user- programmable modes ?doze, nap and sleep ?which progressively reduce the power drawn by the processor. these low-power microprocessors offer dynamic power management to selectively activate functional units as they are needed by the executing instructions. both microprocessors also provide a thermal assist unit and instruction cache throttling for software-controllable thermal management. 32b/64b data 32b address bus interface unit l2 tags system bus fsram integer unit floating point unit i mmu inst. cache d mmu data cache load/ store unit dispatch unit completion unit branch unit gen reg file gen rename fpu reg file l2 cache port (755 only) mpc755fact/d rev. 0 fact sheet m otorola mpc755 and mpc745 p ower pc m icroprocessors motorola mpc755 powerpc microprocessor mpc755/745 microprocessor block diagram
cache and mmu support the mpc755/745 microprocessors have separate 32-kbyte, physically-addressed instruction and data caches. both caches can be locked in part or whole to provide storage of critical data, key performance algorithms, or code loops for fast response time. the mpc755 microprocessor? dedicated l2 cache interface with on-chip l2 tags (up to 1mb) features support for direct-mapped sram mode, physically-mapped sram mode, a fast (typically 1/2 core speed) interface to memory, instruction-only or data-only modes, and parity checking on both l2 address and data. mpc755/745 microprocessors contain separate memory management units (mmus) for instructions and data, supporting 4 petabytes (2 52 ) of virtual memory and 4 gigabytes (2 32 ) of physical memory. both feature eight instruction block address translation (ibat) and eight data block address translation (dbat) registers. access privileges and memory protection are controlled on block or page granularities. large, 128-entry translation lookaside buffers (tlbs) provide efficient physical address translation and support for virtual-memory management on both page- and variable-sized blocks. both hardware and software tablewalks are provided for the tlbs. flexible bus interface mpc755/745 microprocessors have a 64-bit data bus with 32-bit mode and a 32-bit address bus. support is included for burst, split and pipelined transactions. the interface provides snooping for data cache coherency. both microprocessors maintain mei coherency protocol in hardware, allowing access to system memory for additional caching bus masters, such as dma devices. contact information motorola offers user? manuals, application notes and sample code for all of its processors. in addition, local support for these products is also provided. this information can be found at: http://motorola.com/powerpc/ for all other inquiries about motorola products, please contact the motorola customer response center at: phone: 800-521-6274 or http://motorola.com/semiconductors powerpc 1xx, 6xx and 7xx part number key 100, 600, or 700 series device number (106, 107, 603, 740, 745, 750, 755) xpc 755 b px 400 l d product code ppc sample xpc xc qualified mpc qualified part/module modifier a alpha (original) b dgo process e 603 enhanced performance p enhanced & lower voltage r 603e in hip3 process c 2:1 (106 only) d 5:2 (106 only) l full spec all modes frequency 2-3 digits application modifier bus ratio r105 t ext. temp. (-40 to 105 ) -or- application relief revision package fe cqfp rx cbga w/o lid px pbga w/o lid zt pbga w/ lid cpu speeds ?internal cpu bus dividers bus interface instructions per clock l2 cache typical/maximum power dissipation die size package process vo l t a g e specint95 (estimated) specfp95 (estimated) other performance execution units l1 cache core-to-l2 frequency 300 and 350 mhz powerpc 745 300-350 mhz x3, x3.5, x4, x4.5, x5, x5.5, x6, x6.5, x7, x7.5, x8, x10 32-bit/64-bit 3 (2 + branch) tbd 51 mm 2 255 pbga 0.22 5lm 1.8/3.3v i/o, 2.0v internal 15.7 @ 350 mhz 11.6 @ 350 mhz 641 mips @ 350 mhz integer(2), floating-point, branch, load/store, system register 32 kbyte instruction 32 kbyte data 300, 350 and 400 mhz 32-bit/64-bit 3 (2 + branch) 256, 512 kbyte 1 mby te 32-kbyte instruction 32-kbyte data tbd 51 mm 2 1:1, 1.5:1, 2:1, 2.5:1, 3:1 360 pbga 0.22 5lm 1.8/3.3v i/o, 2.0v internal 18.1 @ 400 mhz 12.3 @ 400 mhz 733 mips @ 400 mhz integer(2), floating-point, branch, load/store, system register x3, x3.5, x4, x4.5, x5, x5.5, x6, x6.5, x7, x7.5, x8, x10 powerpc 755 300-400 mhz powerpc 755/745 cpu summary ?2000 motorola, inc. all rights reserved. printed in the u.s.a. motorola and the are registered trademarks and altivec is a trademark of of motorola, inc. powerpc, the powerpc logo, powerpc 603e, powerpc 740 and powerpc 750 are trademarks of international business machines corporation, used under license therefrom. this document contains information on a new product under development. specifications and information herein are subject to change without notice. 1atx45747-0 printed in usa 5/00 hibbert litrisc-uccj
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